Universität Paderborn » SFB 901 » Events


Talk given by Prof. David Andrews (University of Arkansas)

Begin: Thu, 30. of Jun 2016 (10:00 AM)
Location: Warburger Str. 100, O4.267

On June 30, 2016, Prof. Dr. David Andrews (University of Arkansas) will give a talk about "JIT Run Time Assembly of Hardware Accelerators" in the context of the SFB 901.

Reconfigurable Computing (RC) is poised to become part of the mainstream computing narrative. Intel acquired Altera and will soon be providing commodity components that integrate FPGAs with Xeon manycore chips.  Unfortunately current state-of-the-art programming languages, design abstractions and design flows used for programming FPGAs still require hardware development skills. Under current design flows any change made to the functionality of an accelerator destined for implementation within an FPGA must be re-synthesized. This places the use of FPGAs outside of the skill set and development flows of todays software  application developers.  In this talk I will discuss our recent work to move FPGAs into the comfort zone for software application programmers. Our objective is to allow software developers to simply compile together hardware accelerators outside of CAD tools and without having to synthesize their design. Our approach allows programmers to compose libraries of pre-synthesized versions of software programming patterns just as if they were using pre-compiled code and creating new software functions. We provide a new virtual machine similar to the JVM that uses a data flow description of how the programming patterns were combined in the application code output by the compiler to map and connect the hardware bitstream executables within an overlay architecture embedded within the reconfigurable fabric. The approach allows programmers to recompile different compositions of programming patterns into different accelerators without having to pass through synthesis. Preliminary results will be provided showing the utility of the approach on Chip Heterogeneous Multiprocessor (CMPs) architectures as well as a reconfigurable cluster with 24 FPGAs in the cloud.