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CRC 901 – On-The-Fly Computing (OTF Computing) Bildinformationen anzeigen

CRC 901 – On-The-Fly Computing (OTF Computing)

Mittwoch, 08.01.2020 | 16.00 Uhr | F0.530, Fürstenallee 11, 33102 Paderborn

Fourth SFB 901 Seminar in winter semester 2019/2020

On January 8, 2020, the 4th SFB 901 seminar in the winter semester will take place.

4:00 - 4:25 subproject B1
Speaker: Jun.-Prof. Dr. Henning Wachsmuth
Title: Style Transfer in Natural Language Processing


In phase 3 of the CRC, subproject B1 deals with the chatbot-based specification and explanation of services in natural language. The style of the explanations is meant to match the style of the user's specifications. In this talk, we will briefly overview the goals of B1 in phase 3. Then, we will give insights into the use of style transfer techniques from natural language processing in the generation of explanations.

4:25 - 4:50 subproject C2
Speaker: Prof. Dr. Christian Plessl
Title: Multi-FPGA Clusters with Hybrid Networks: Foundations and Potential for OTF Applications


Today, packet-switched networks constitute the communication backbone for both, general purpose data and high-performance computing centers. Through a hierarchical connection of switches it is possible to design flexible and highly scalable networks that can be statically, i.e. at design time, configured to the requirements for bandwidth and number of endpoints. While tiered packet-switched networks have clear advantages in flexibility, scalability, and economy of scale they can suffer from latency and congestion introduced by multi-hop routing and a bulk communication model.

For the third phase of SFB 901, we consider FPGA clusters with hybrid networks, where each node is attached to a packet switched network, but also to a circuit-switched network that can establish point-to-point connections between endpoints. This network is implemented with a high-radix full-crossbar optical switch. This communication model is suitable for a streaming dataflow execution model that is preferable for FPGAs. In this talk I will introduce the properties of both networks and discuss challenges for dynamically mapping OTF application to an FPGA cluster with hybrid networks, which will be the subject of our further studies.

5:00 - 5:45 parallel Session

Room: F0.530
Speaker: Joschka Kersting, subproject B1
Title: From Static to Dialogue-based Requirements Elaboration


B1 will develop knowledge resources and procedures to compensate initial user input deficits (typos, ambiguity, vagueness, incompleteness) by translating abstract error descriptions into concrete target group-oriented queries. In order to model the knowledge used for this, we will develop a semi-automated, data-driven linked open-data approach. In the talk, we outline how the planned knowledge base must look like and explain the NLP challenges in close proximity to the given scenarios.

Room: F0.231
Speaker: Heinrich Riebler, subproject C2
Title: Using On-the-Fly Code Generation to Transparently Accelerate Applications in Heterogeneous Systems


Multi-accelerator platforms combine CPUs and different accelerator architectures within a single compute node. Such systems are capable of processing parallel workloads very efficiently, while being more energy efficient than regular systems consisting of CPUs only. However, the architectures of such systems are diverse, forcing developers to port applications to each accelerator using different programming languages, models, tools and compilers. Developers not only require domain-specific knowledge, but also need to understand the low-level accelerator details, leading to an increase in the design effort and costs.

To tackle this challenge, we propose a compilation approach and a practical realization that is completely transparent to the user. Our tool flow is able to automatically analyze a sequential CPU application, detect computational hotspots and generate parallel OpenCL host and kernel code. The potential is demonstrated by offloading hotspots to different OpenCL-enabled resources (currently CPU, GPGPU and the manycore Intel Xeon Phi) for a broad set of benchmark applications. We present an in-depth evaluation of our approach in terms of performance gains and energy savings taking into account all static and dynamic overheads.



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